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PRELIMINARY
1 Mbit (128 K x 8) Serial (I C) nvSRAM
Features

CY14C101J CY14B101J, CY14E101J 2
1-Mbit nonvolatile static random access memory (nvSRAM) Internally organized as 128 K x 8 STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE) RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL) Automatic STORE on power-down with a small capacitor (except for CY14X101J1) High reliability

Industry standard configurations Operating voltages: * CY14C101J: VCC = 2.4 V to 2.6 V * CY14B101J: VCC = 2.7 V to 3.6 V * CY14E101J: VCC = 4.5 V to 5.5 V Industrial temperature 8- and 16-pin small outline integrated circuit (SOIC) package Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C101J/CY14B101J/CY14E101J combines a 1-Mbit nvSRAM[1] with a nonvolatile element in each memory cell. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14X101J1). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.
Infinite read, write, and RECALL cycles 1 million STORE cycles to QuantumTrap Data retention: 20 years at 85 C
High speed I2C interface Industry standard 100 kHz and 400 kHz speed Fast-mode Plus: 1 MHz speed High speed: 3.4 MHz Zero cycle delay reads and writes Write protection Hardware protection using Write Protect (WP) pin Software block protection for 1/4, 1/2, or entire array I2C access to special functions Nonvolatile STORE/RECALL 8 byte serial number Manufacturer ID and Product ID Sleep mode Low power consumption Average active current of 1 mA at 3.4 MHz operation Average standby mode current of 150 uA Sleep mode current of 8 uA
Configuration
Feature AutoStore Software STORE Hardware STORE CY14X101J1 No Yes No CY14X101J2 Yes Yes No CY14X101J3 Yes Yes Yes
Logic Block Diagram
VCC VCAP
Serial Number 8x8 Manufacture ID/ Product ID Memory Control Register Command Register Quantrum Trap 128 K x 8 SRAM 128 K x 8 STORE RECALL
Power Control Block Sleep SDA SCL A2, A1 WP
2
Control Registers Slave Memory Slave Memory Address and Data Control
I C Control Logic Slave Address Decoder
Note 1. Serial (I2C) nvSRAM is referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation Document #: 001-54050 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 19, 2011
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Contents
Pinouts .............................................................................. 3 I2C Interface ...................................................................... 4 Protocol Overview ............................................................ 4 I2C Protocol - Data Transfer....................................... 4 Data Validity ...................................................................... 5 START Condition (S) ........................................................ 5 STOP Condition (P) .......................................................... 5 Repeated START (Sr) ....................................................... 5 Byte Format....................................................................... 5 Acknowledge/No-acknowledge....................................... 6 High-Speed Mode (Hs-mode) .......................................... 6 Serial Data Format in Hs-mode................................... 6 Slave Device Address ...................................................... 7 Memory Slave Device ................................................. 7 Control Registers Slave Device................................... 8 Memory Control Register ............................................ 8 Command Register ..................................................... 8 Write Protection (WP)....................................................... 9 AutoStore Operation ........................................................ 9 Hardware STORE and HSB pin Operation ..................... 9 Hardware RECALL (Power-Up) ................................ 10 Write Operation............................................................... 10 Read Operation............................................................... 10 Memory Slave Access.................................................... 10 Write nvSRAM........................................................... 10 Current nvSRAM Read.............................................. 11 Random Address Read ............................................. 13 Control Registers Slave ................................................. 14 Write Control Registers ................................................. Current Control Registers Read ................................ Random Control Registers Read .............................. Serial Number ........................................................... Executing Commands Using Command Register....... Best Practices................................................................. Maximum Ratings........................................................... Operating Range............................................................. DC Electrical Characteristics ........................................ Data Retention and Endurance .................................... Thermal Resistance........................................................ AC Test Conditions ........................................................ AC Switching Characteristics ....................................... nvSRAM Specifications ................................................. Software Controlled STORE/RECALL Cycles.............. Hardware STORE Cycle ................................................. Ordering Information...................................................... Ordering Code Definitions ......................................... Package Diagrams.......................................................... Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Document History Page ................................................ Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 14 15 15 16 17 18 19 19 19 20 20 21 22 23 24 25 26 27 28 30 30 30 31 32 32 32 32
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Pinouts
Figure 1. Pin Diagram - 8-Pin SOIC
[2]
NC
1 2 3 4 CY14X101J1 Top View not to scale
8 7 6 5
VCC WP SCL SDA
VCAP
1 2 3 4 CY14X101J2 Top View not to scale
8 7 6 5
VCC WP SCL SDA
A1 A2 VSS
A1 A2 VSS
Figure 2. Pin Diagram - 16-Pin SOIC
NC NC NC NC WP NC NC VSS
[2]
1 2 3 4 5 6 7 8 CY14X101J3 Top View not to scale
16 15 14 13 12 11 10 9
VCC NC VCAP A2 SDA SCL A1 HSB
Table 1. Pin Definitions Pin Name SCL SDA WP A2-A1 HSB I/O Type Input Input/Output Input Input Input/Output Description Clock. Runs at speeds up to a maximum of fSCL. I/O. Input/Output of data through I2C interface. Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can be left open if not connected. Slave Address. Defines the slave address for I2C. This pin is internally pulled LOW and hence can be left open if not connected. Hardware STORE Busy Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (External pull up resistor connection optional). Input: Hardware STORE implemented by pulling this pin LOW externally. AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as no connect. It must never be connected to ground. No connect. This pin is not connected to the die. Ground. Power supply.
VCAP
Power supply
NC VSS VCC
No connect Power supply Power supply
Note 2. This pin is reserved for lower densities.
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PRELIMINARY
I2C Interface
I2C bus consists of two lines - serial clock line (SCL) and serial data line (SDA) that carry information between multiple devices on the bus. I2C supports multi-master and multi-slave configurations. The data is transmitted from the transmitter to the receiver on the SDA line and is synchronized with the clock SCL generated by the master. The SCL and SDA lines are open-drain lines and are pulled up to VCC using resistors. The choice of a pull-up resistor on the system depends on the bus capacitance and the intended speed of operation. The master generates the clock and all the data IOs are transmitted in synchronization with this clock. The CY14X101J supports up to 3.4 MHz clock speed on SCL line.
CY14C101J CY14B101J, CY14E101J
Protocol Overview
This device supports only a 7-bit addressable scheme. The master generates a START condition to initiate the communication followed by broadcasting a slave select byte. The slave select byte consists of a seven bit address of the slave that the master intends to communicate with and R/W bit indicating a read or a write operation. The selected slave responds to this with an acknowledgement (ACK). After a slave is selected, the remaining part of the communication takes place between the master and the selected slave device. The other devices on the bus ignore the signals on the SDA line till a STOP or Repeated START condition is detected. The data transfer is done between the master and the selected slave device through the SDA pin synchronized with the SCL clock generated by the master.
address and eighth bit (R/W) indicating a read (1) or a write (0) operation. All signals are transmitted on the open-drain SDA line and are synchronized with the clock on SCL line. Each byte of data transmitted on the I2C bus is acknowledged by the receiver by holding the SDA line LOW on the ninth clock pulse. The request for write by the master is followed by the memory address and data bytes on the SDA line. The writes can be performed in burst-mode by sending multiple bytes of data. The memory address increments automatically after receiving /transmitting of each byte on the falling edge of 9th clock cycle. The new address is latched just prior to sending/receiving the acknowledgment bit. This allows the next sequential byte to be accessed with no additional addressing. On reaching the last memory location, the address rolls back to 0x00000 and writes continue. The slave responds to each byte sent by the master during a write operation with an ACK. A write sequence can be terminated by the master generating a STOP or Repeated START condition. A read request is performed at the current address location (address next to the last location accessed for read or write). The memory slave device responds to a read request by transmitting the data on the current address location to the master. A random address read may also be performed by first sending a write request with the intended address of read. The master must abort the write immediately after the last address byte and issue a Repeated START or STOP signal to prevent any write operation. The following read operation starts from this address. The master acknowledges the receipt of one byte of data by holding the SDA pin LOW for the ninth clock pulse. The reads can be terminated by the master sending a no-acknowledge (NACK) signal on the SDA line after the last data byte. The no-acknowledge signal causes the CY14X101J to release the SDA line and the master can then generate a STOP or a Repeated START condition to initiate a new operation.
I2C Protocol - Data Transfer
Each transaction in I2C protocol starts with the master generating a START condition on the bus, followed by a seven bit slave
Figure 3. System Configuration using Serial (I2C) nvSRAM
Vcc
RPmin = (VCC - VOLmax) / IOL RPmax = tr / Cb
SDA
Microcontroller
SCL Vcc A1 A2 Vcc SCL SDA WP A1 A2 SCL SDA WP A1 A2 SCL SDA WP
CY14X101J #0
CY14X101J #1
CY14X101J #3
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The state of the data line can only change when the clock on the SCL line is LOW for the data to be valid. There are only two conditions under which the SDA line may change state with SCL line held HIGH, that is, START and STOP condition. The START and STOP conditions are generated by the master to signal the beginning and end of a communication sequence on the I2C bus.
STOP Condition (P)
A LOW to HIGH transition on the SDA line while SCL is HIGH indicates a STOP condition. This condition indicates the end of the ongoing transaction. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again after the STOP condition.
START Condition (S)
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. Every transaction in I2C begins with the master generating a START condition.
Repeated START (Sr)
If an Repeated START condition is generated instead of a Stop condition the bus continues to be busy. The ongoing transaction on the I2C lines is stopped and the bus waits for the master to send a slave ID for communication to restart.
Figure 4. START and STOP Conditions
full pagewidth
SDA
SDA
SCL S START Condition P STOP Condition
SCL
Figure 5. Data Transfer on the I2C Bus
handbook, full pagewidth
P Sr
SDA MSB Acknowledgement signal from slave Acknowledgement signal from receiver
SCL
S or Sr
1
2
7
8
9 ACK
1
2
3-8
9 ACK
Sr or P STOP or Repeated START condition
START or Repeated START condition
Byte complete, interrupt within slave
Clock line held LOW while interrupts are serviced
Byte Format
Each operation in I2C is done using 8 bit words. The bits are sent in MSB first format on SDA line and each byte is followed by an ACK signal by the receiver. An operation continues till a NACK is sent by the receiver or STOP or Repeated START condition is generated by the master The SDA line must remain stable when the clock (SCL) is HIGH except for a START or STOP condition.
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Acknowledge/No-acknowledge
After transmitting one byte of data or address, the transmitter releases the SDA line. The receiver pulls the SDA line LOW to acknowledge the receipt of the byte. Every byte of data transferred on the I2C bus needs to be responded with an ACK signal by the receiver to continue the operation. Failing to do so is considered as a NACK state. NACK is the state where receiver does not acknowledge the receipt of data and the operation is aborted. NACK can be generated by master during a READ operation in following cases:
The master generates a NACK to abort the READ sequence. After a NACK is issued by the master, nvSRAM slave releases control of the SDA pin and the master is free to generate a Repeated START or STOP condition.
NACK can be generated by nvSRAM slave during a WRITE operation in following cases: nvSRAM did not receive valid data due to noise. The master tries to access write protected locations on the nvSRAM. Master must restart the communication by generating a STOP or Repeated START condition.
The master did not receive valid data due to noise Figure 6. Acknowledge on the I2C Bus
handbook, full pagewidth
DATA OUTPUT BY MASTER not acknowledge (A) DATA OUTPUT BY SLAVE acknowledge (A) SCL FROM MASTER S START condition clock pulse for acknowledgement 1 2 8 9
High-Speed Mode (Hs-mode)
In Hs-mode, nvSRAM can transfer data at bit rates of up to 3.4 bit/s. A master code (0000 1XXXb) must be issued to place the device into high speed mode. This enables master slave communication for speed upto 3.4 MHz. A stop condition exits Hs-mode.
Serial Data Format in Hs-mode
Serial data transfer format in Hs-mode meets the standard-mode I2C-bus specification. Hs-mode can only commence after the following conditions (all of which are in F/S-modes): 1. START condition (S) 2. 8-bit master code (0000 1XXXb) 3. No-acknowledge bit (A)
Figure 7. Data transfer format in Hs-mode
handbook, full pagewidth
F/S-mode S MASTER CODE
Hs-mode A Sr SLAVE ADD. R/W A DATA n (bytes+ ack.) A/A P
F/S-mode
Hs-mode continues
Sr SLAVE ADD.
Single and multiple-byte reads and writes are supported. After the device enters into Hs-mode, data transfer continues in Hs-mode until stop condition is sent by master device. The slave switches back to F/S-mode after a STOP condition (P). To
continue data transfer in Hs-mode, the master sends Repeated START (Sr). See Figure 13 on page 11 and Figure 16 on page 12 for Hs-mode timings for read and write operation.
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Slave Device Address
Every slave device on an I2C bus has a device select address. The first byte after START condition contains the slave device address with which the master intends to communicate. The seven MSBs are the device address and the LSB (R/W bit) is used for indicating Read or Write operation. The CY14X101J reserves two sets of upper 4 MSBs [7:4] in slave device address field for accessing Memory and Control Registers. The Table 2. Slave device Addressing Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
accessing mechanism is described in Memory Slave Device on page 7. The nvSRAM product provides two different functionalities: Memory and Control Registers functions (such as serial number and product ID). The two functions of the device are accessed through different slave device addresses. The first four most significant bits [7:4] in the device address register are used to select between the nvSRAM functions.
nvSRAM Bit 0 Function Select
CY14X101J Slave Devices Memory, 128 K x 8
1
0
1
0
Device Select ID
A16
R/W Selects Memory
Control Registers - Memory Control Register, 1 x 8 0 0 1 1 Device Select ID X R/W Selects Control Registers - Serial Number, 8 x 8 - Device ID, 4 x 8 - Command Register, 1 x 8
Memory Slave Device
The nvSRAM device is selected for Read/Write if the master issues the slave address as 1010b followed by two bits of device select. If slave address sent by the master matches with the Memory Slave device address then depending on the R/W bit of the slave address, data is either read from (R/W = `1') or written to (R/W = '0') the nvSRAM. The address length for CY14X101J is 17 bits and thus it requires 3 address bytes to map the entire memory address location. To save extra byte for memory addressing, the 17th bit (A16) is mapped to the slave address select bit (A0). The dedicated two address bytes represent bit A0 to A15.
Figure 8. Memory Slave Device Address
MSB handbook, halfpage 1 0 1 0 A2 A1 LSB A16 R/W
MSB of Address
Slave ID
Device Select
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Control Registers Slave Device
The Control Registers Slave device includes the Serial Number, Product ID, Memory Control and Command Register. The nvSRAM Control Register Slave device is selected for Read/Write if the master issues the Slave address as 0011b followed by two bits of device select. Then, depending on the R/W bit of the Slave address, data is either read from (R/W = `1') or written to (R/W = `0') the device. Figure 9. Control Registers Slave Device Address
MSB handbook, halfpage 0 0 1 1 A2 A1 X LSB R/W
Table 5. Block Protection Level 0 1/4 1/2 1
BP1:BP0 00 01 10 11
Block Protection None 0x18000-0x1FFFF 0x10000-0x1FFFF 0x00000-0x1FFFF
Slave ID
Device Select
Table 3. Control Registers map Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0xAA Description Memory Control Register Serial Number 8 Bytes Read/Write Details Read/Write Contains Block Protect Bits and Serial Number Lock bit Read/Write Programmable Serial (Read only Number. Locked by when SNL setting the Serial is set) Number lock bit in Memory Control Register to `1'.
SNL (S/N Lock) Bit: Serial Number Lock bit (SNL) is used to lock the serial number. Once the bit is set to `1', the serial number registers are locked and no modification is allowed. This bit cannot be cleared to `0'. The serial number is secured on the next STORE operation (Software STORE or AutoStore). If AutoStore is not enabled, user must perform Software STORE operation to secure the lock bit status. If a STORE was not performed, the serial number lock bit will not survive power cycle. The default value shipped from the factory for SNL is `0'.
Command Register
The Command Register resides at address "AA" of the Control Registers Slave device. This is a write only register. The byte written to this register initiates a STORE, RECALL, AutoStore Enable, AutoStore Disable and sleep mode operation as listed in Table 6. Refer to Serial Number on page 16 for details on how to execute a command register byte. Table 6. Command Register bytes Data Byte [7:0] 0011 1100 0110 0000 0101 1001 0001 1001 1011 1001
Command STORE RECALL ASENB ASDISB SLEEP
Description STORE SRAM data to nonvolatile memory RECALL data from nonvolatile memory to SRAM Enable AutoStore Disable AutoStore Enter Sleep Mode for low power consumption
Device ID
Read only Device ID is factory programmed
Reserved Command Register
Reserved Reserved Write only Allows commands for STORE, RECALL, AutoStore Enable/Disable, SLEEP Mode
Memory Control Register
Memory Control Register contains the following bits: Table 4. Memory Control Register Bits Bit 7 0

STORE: Initiates nvSRAM Software STORE. The nvSRAM cannot be accessed for tSTORE time after this instruction has been executed. When initiated, the device performs a STORE operation regardless of whether a write has been performed since the last NV operation. After the tSTORE cycle time is completed, the SRAM is activated again for read and write operations. RECALL: Initiates nvSRAM Software RECALL. The nvSRAM cannot be accessed for tRECALL time after this instruction has been executed. The RECALL operation does not alter the data in the nonvolatile elements. A RECALL may be initiated in two ways: Hardware RECALL, initiated on power-up; and Software RECALL, initiated by a I2C RECALL instruction. ASENB: Enables nvSRAM AutoStore. The nvSRAM cannot be accessed for tSS time after this instruction has been executed. This setting is not nonvolatile and needs to be followed by a manual STORE sequence if this is desired to survive power cycle. The part comes from the factory with AutoStore Enabled.
Bit 6 SNL (0)
Bit 5 0
Bit 4 0
Bit 3 BP1 (0)
Bit 2 BP0 (0)
Bit 1 0
Bit 0 0
BP1:BP0: Block Protect bits are used to protect 1/4, 1/2 or full memory array. These bits can be written through a write instruction to the 0x00 location of Control Register Slave device. However, any STORE cycle causes transfer of SRAM data into a nonvolatile cell regardless of whether or not the block is protected. The default value shipped from the factory for BP0 and BP1 is `0'.
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot be accessed for tSS time after this instruction has been executed. This setting is not nonvolatile and needs to be followed by a manual STORE sequence if this is desired to survive power cycle.
Note If AutoStore is disabled and VCAP is not required, it is required that the VCAP pin is left open. VCAP pin must never be connected to ground. Power-Up RECALL operation cannot be disabled in any case.
voltage on the VCC pin drops below VSWITCH during power-down, the device inhibits all memory accesses to nvSRAM and automatically performs a conditional STORE operation using the charge from the VCAP capacitor. The AutoStore operation is not initiated if no write cycle has been performed since the last STORE or RECALL. Note If a capacitor is not connected to VCAP pin, AutoStore must be disabled by issuing the AutoStore Disable instruction specified in "Command Register" on page 8. If AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This will corrupt the data stored in nvSRAM Figure 10 shows the proper connection of the storage capacitor (VCAP) for AutoStore operation. Refer to DC Electrical Characteristics on page 19 for the size of the VCAP.
SLEEP: SLEEP instruction puts the nvSRAM in a sleep mode. When the SLEEP instruction is registered, the nvSRAM performs a STORE operation to secure the data to nonvolatile memory and then enters into sleep mode. Whenever nvSRAM enters into sleep mode, it initiates non volatile STORE cycle which results in losing an endurance cycle per sleep command execution. A STORE cycle starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle.
Hardware STORE and HSB pin Operation
The HSB pin in CY14X101J is used to control and acknowledge STORE operations. If no STORE or RECALL is in progress, this pin can be used to request a Hardware STORE cycle. When the HSB pin is driven LOW, device conditionally initiates a STORE operation after tDELAY duration. An actual STORE cycle starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle. Reads and Writes to the memory are inhibited for tSTORE duration or as long as HSB pin is LOW. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 k pull-up resistor. Note For successful last data byte STORE, a hardware STORE should be initiated at least one clock cycle after the last data bit D0 is received. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB pin unconnected if not used. Figure 10. AutoStore Mode
VCC
The nvSRAM enters into sleep mode as follows: 1. The Master sends a START command 2. The Master sends Control Registers Slave device ID with I2C Write bit set (R/W = '0') 3. The Slave (nvSRAM) sends an ACK back to the Master 4. The Master sends Command Register address (0xAA) 5. The Slave (nvSRAM) sends an ACK back to the Master 6. The Master sends Command Register byte for entering into Sleep mode 7. The Slave (nvSRAM) sends an ACK back to the Master 8. The Master generates a STOP condition. Once in Sleep mode the device starts consuming IZZ current tSLEEP time after SLEEP instruction is registered. The device is not accessible for normal operations until it is out of sleep mode. The nvSRAM wakes up after tWAKE duration after the device slave address is transmitted by the master. Transmitting any of the two slave addresses wakes the nvSRAM from Sleep mode. The nvSRAM device is not accessible during tSLEEP and tWAKE interval, and any attempt to access the nvSRAM device by the master is ignored and nvSRAM sends NACK to the master. As an alternative method of determining when the device is ready, the master can send read or write commands and look for an ACK.
Write Protection (WP)
The WP pin is an active high pin and protects entire memory and all registers from write operations. To inhibit all the write operations, this pin must be held high. When this pin is high, all memory and register writes are prohibited and address counter is not incremented. This pin is internally pulled LOW and hence can be left open if not used.
0.1 uF VCC
VCAP VCAP
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which automatically stores the SRAM data to QuantumTrap cells during power-down. This STORE makes use of an external capacitor (VCAP) and enables the device to safely STORE the data in the nonvolatile memory when power goes down. During normal operation, the device draws current from VCC to charge the capacitor connected to the VCAP pin. When the Document #: 001-54050 Rev. *D
VSS
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CY14C101J CY14B101J, CY14E101J
Hardware RECALL (Power-Up)
During power-up, when VCC crosses VSWITCH, an automatic RECALL sequence is initiated which transfers the content of nonvolatile memory on to the SRAM. The data would previously have been stored on the nonvolatile memory through a STORE sequence. A Power-Up RECALL cycle takes tFA time to complete and the memory access is disabled during this time. HSB pin can be used to detect the Ready status of the device.
More details on write instruction are provided in Section "Memory Slave Access" on page 10.
Read Operation
If the last bit of the slave device address is `1', a read operation is assumed and the nvSRAM takes control of the SDA line immediately after the slave device address byte is sent out by the master. The read operation starts from the current address location (the location following the previous successful write or read operation). When the last address is reached, the address counter loops back to the first address. In case of the Control Register Slave, whenever a burst read is performed such that it flows to a non-existent address, the reads operation will loop back to 0x00. This is applicable, in particular for the Command Register. There are the following ways to end a read operation: 1. The Master issues a NACK on the 9th clock cycle followed by a STOP or a Repeated START condition on the 10th clock cycle. 2. Master generates a STOP or Repeated START condition on the 9th clock cycle. More details on write instruction are provided in Section "Memory Slave Access" on page 10
Write Operation
The last bit of the slave device address indicates a read or a write operation. In case of a write operation, the slave device address is followed by the memory or register address and data. A write operation continues as long as a STOP or Repeated START condition is generated by the master or if a NACK is issued by the nvSRAM. A NACK is issued from the nvSRAM under the following conditions: 1. A valid Device ID is not received. 2. A write (burst write) access to a protected memory block address returns a NACK from nvSRAM after the data byte is received. However, the address counter is set to this address and the following current read operation starts from this address. 3. A write/random read access to an invalid or out-of-bound memory address returns a NACK from the nvSRAM after the address is received. The address counter remains unchanged in such a case. 4. A write to the Command Register with an invalid command. This operation would return a NACK from the nvSRAM. After a NACK is sent out from the nvSRAM, the write operation is terminated and any data on the SDA line is ignored till a STOP or a Repeated START condition is generated by the master. For example, consider a case where burst write access is performed on Control Register Slave address 0x01 for writing the serial number and continued to the address 0x09, which is a read only register. The device returns a NACK and address counter will not be incremented. A following read operation will be started from the address 0x09. Further, any write operation which starts from a write protected address (say, 0x09) will be responded by the nvSRAM with a NACK after the data byte is sent and set the address counter to this address. A following read operation will start from the address 0x09 in this case also. Note In case the user tries to read/write access an address that does not exist (for example 0x0D in Control Register Slave), nvSRAM responds with a NACK immediately after the out-of-bound address is transmitted. The address counter remains unchanged and holds the previous successful read or write operation address. A write operation is performed internally with no delay after the eighth bit of data is transmitted. If a write operation is not intended, the master must terminate the write operation before the eighth clock cycle by generating a STOP or Repeated START condition.
Memory Slave Access
The following sections describe the data transfer sequence required to perform Read or Write operations from nvSRAM.
Write nvSRAM
Each write operation consists of a slave address being transmitted after the start condition. The last bit of slave address must be set as `0' to indicate a Write operation. The master may write one byte of data or continue writing multiple consecutive address locations while the internal address counter keeps incrementing automatically. The address register is reset to 0x00000 after the last address in memory is accessed. The write operation continues till a STOP or Repeated START condition is generated by the master or a NACK is issued by the nvSRAM. A write operation is executed only after all the 8 data bits have been received by the nvSRAM. The nvSRAM sends an ACK signal after a successful write operation. A write operation may be terminated by the master by generating a STOP condition or a Repeated START operation. If the master desires to abort the current write operation without altering the memory contents, this should be done using a START/STOP condition prior to the 8th data bit. If the master tries to access a write protected memory address on the nvSRAM, a NACK is returned after the data byte intended to write the protected address is transmitted and address counter will not be incremented. Similarly, in a burst mode write operation, a NACK is returned when the data byte that attempts to write a protected memory location and address counter will not be incremented.
Document #: 001-54050 Rev. *D
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Figure 11. Single-Byte Write into nvSRAM (except Hs-mode)
S T A R T S 1
By Master
Memory Slave Address
Address MSB
Address LSB
Data Byte
S T 0 P P
SDA Line
0
1
0 A2 A1 A16 0
By nvSRAM A A A A
Figure 12. Multi-Byte Write into nvSRAM (except Hs-mode)
S T A R Memory Slave Address T
S 1 0 1 0 A2 A1 A16 0
By Master SDA Line By nvSRAM
Address MSB
Address LSB
Data Byte 1
Data Byte N
S T 0 P
P
A
A
A
A
~ ~
A
Figure 13. Single-Byte Write into nvSRAM (Hs-mode)
S T A R T
By Master SDA Line By nvSRAM
Hs-mode command 01 XXX
Memory Slave Address Sr 1 0 1 0 A2 A1 A16 0
Address MSB
Address LSB
Data Byte
S T 0 P P
S000
A
A
A
A
A
Figure 14. Multi-Byte Write into nvSRAM (Hs-mode)
S T A R T
By Master
Hs-mode command 01 XXX
Memory Slave Address Sr 1 0 1 0 A2 A1 A16 0
Address MSB
Address LSB
Data Byte 1
SDA Line By nvSRAM
S000
A
A
A S T 0 P P
A
A
By Master SDA Line
Data Byte 2
Data Byte 3
Data Byte N
By nvSRAM
A
A
~ ~
A
Current nvSRAM Read
Each read operation starts with the master transmitting the nvSRAM slave address with the LSB set to `1' to indicate "Read". The reads start from the address on the address counter. The address counter is set to the address location next to the last accessed with a "Write" or "Read" operation. The master may
terminate a read operation after reading 1 byte or continue reading addresses sequentially till the last address in the memory after which the address counter rolls back to the address 0x00000. The valid methods of terminating read access are described in Section "Read Operation" on page 10. Note A16-bit is ignored while using the current nvSRAM read.
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~ ~
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Figure 15. Current Location Single-Byte nvSRAM Read (except Hs-mode)
S T A R T S 1
By Master
Memory Slave Address
A
S T 0 P P
SDA Line By nvSRAM
0
1
0
A2 A1 X
1
A
Data Byte
Figure 16. Current Location Multi-Byte nvSRAM Read (except Hs-mode)
S T A R T S 1
A Memory Slave Address
A
By Master SDA Line
S T 0 P P
By nvSRAM A
~ ~
0
1
0 A2 A1 X
1
Data Byte
Data Byte N
Figure 17. Current Location Single-Byte nvSRAM Read (Hs-mode)
S T A R T
By Master SDA Line By nvSRAM
Hs-mode command 01 XXX
Memory Slave Address Sr 1 0 1 0 A2 A1 X 1 Data Byte
S AT 0 P P
S000
A
A
Figure 18. Current Location Multi-Byte nvSRAM Read (Hs-mode)
S T A R T
By Master
A Hs-mode command 01 XXX Memory Slave Address
A
S T 0 P P
~ ~
SDA Line
S000
Sr 1 0
1 0 A2 A1 X 1
By nvSRAM A
Data Byte A
Data Byte N
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Random Address Read
A random address read is performed by first initiating a write operation and generating a Repeated START immediately after the last address byte is acknowledged. The address counter is set to this address and the next read access to this slave will initiate read operation from here. The master may terminate a read operation after reading 1 byte or continue reading addresses sequentially till the last address in the memory after which the address counter rolls back to the start address 0x00000. Figure 19. Random Address Single-Byte Read (except Hs-mode)
S T A R T
S
A
By Master
Memory Slave Address
1 0 A2 A1 A16 0
Address MSB
Address LSB
Sr 1
Memory slave Address
0 1 0 A2 A1 X
S T 0 P
P
SDA Line By nvSRAM
1
0
1
Data Byte
A A A A
Figure 20. Random Address Multi-Byte Read (except Hs-mode)
S T A R T
S
A
By Master
Memory Slave Address
1 0 A2 A1 A16 0
Address MSB
Address LSB
Sr 1
Memory slave Address
0 1 0 A2 A1 X
SDA Line By nvSRAM
1
0
1
Data Byte 1
A A
S T 0 P
P
A
A
A
Data Byte N
Figure 21. Random Address Single-Byte Read (Hs-mode)
By Master
S T A R T
Hs-mode command 01 XXX
Memory Slave Address Sr 1 0 1 0 A2 A1 A16 0
Address MSB
Address LSB
Memory Slave Address Sr 1 0 1 0 A2 A1 X 1
By nvSRAM A S T A0 P P Data Byte A A A A
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~ ~
SDA Line
S000
~ ~
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CY14C101J CY14B101J, CY14E101J
Figure 22. Random Address Multi-Byte Read (Hs-mode)
S T A R T
By Master SDA Line By nvSRAM
HS-mode command 01 XXX
Memory Slave Address Sr 1 0 1 0 A2 A1 A16 0
Address MSB
Address LSB
Memory Slave Address Sr 1 0 1 0 A2 A1 X 1
A
A S T 0 P P Data Byte N
A
A
A
A
A
Data Byte
Control Registers Slave
The following sections describes the data transfer sequence required to perform Read or Write operations from Control Registers Slave.
~ ~
Write Control Registers
To write the Control Registers Slave, the master transmits the Control Registers Slave address after generating the START condition. The write sequence continues from the address location specified by the master till the master generates a STOP condition or the last writeable address location. If a non writeable address location is accessed for write operation during a normal write or a burst, the slave generates a NACK after the data byte is sent and the write sequence terminates. Any following data bytes are ignored and the address counter is not incremented. If a write operation is performed on the Command Register (0xAA), the following current read operation also begins from the
first address (0x00) as in this case, the current address is an out-of-bound address. The address is not incremented and the next current read operation begins from this address location. If a write operation is attempted on an out-of-bound address location, the nvSRAM sends a NACK immediately after the address byte is sent. Further, if the serial number is locked, only two addresses (0xAA or Command Register, and 0x00 or Memory Control Register) are writeable in the Control Registers Slave. On a write operation to any other address location, the device will acknowledge command byte and address bytes but it returns a NACK from the Control Registers Slave for data bytes. In this case, the address will not be incremented and a current read will happen from the last acknowledged address. The nvSRAM Control Registers Slave sends a NACK when an out of bound memory address is accessed for write operation, by the master. In such a case, a following current read operation begins from the last acknowledged address.
Figure 23. Single-Byte Write into Control Registers
S T A R T S 0 0
By Master
Control Registers Slave Address
Control Register Address
Data Byte
S T 0 P P
SDA Line By nvSRAM
1
1 A2 A1 X
0
A
A
A
Figure 24. Multi-Byte Write into Control Registers
S T A R T S 0 0 S T 0 P P
By Master
Control Registers Slave Address
Control Register Address
Data Byte
Data Byte N
SDA Line By nvSRAM
1
1 A2 A1 X
0
A
A
~ ~
A
A
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~ ~
S000
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CY14C101J CY14B101J, CY14E101J
Current Control Registers Read
A read of Control Registers Slave is started with master sending the Control Registers Slave address after the START condition with the LSB set to `1'. The reads begin from the current address which is the next address to the last accessed location. The reads to Control Registers Slave continues till the last readable address location and loops back to the first location (0x00). Note that the Command Register is a write only register and is not accessible through the sequential read operations. If a burst read operation begins from the Command Register (0xAA), the address counter wraps around to the first address in the register map (0x00). Figure 25. Control Registers Single-Byte Read
S T A R T S 0 0
By Master
Control Registers Slave Address
A
S T 0 P P
SDA Line By nvSRAM
1
1 A2 A1
X
1
Data Byte
A
Figure 26. Current Control Registers Multi-Byte Read
S T A R T S 0 0
By Master
Control Registers Slave Address
A
A
S T 0 P P
SDA Line By nvSRAM
1
Data Byte A
~ ~
1
1 A2 A1 X
Data Byte N
Random Control Registers Read
A read of random address may be performed by initiating a write operation to the intended location of read and immediately following with a Repeated START operation. The reads to Control Registers Slave continues till the last readable address location and loops back to the first location (0x00). Note that the Command Register is a write only register and is not accessible through the sequential read operations. A random read starting at the Command Register (0xAA) loops back to the first address in the Control Registers map (0x00). If a random read operation is initiated from an out-of-bound memory address, the nvSRAM sends a NACK after the address byte is sent
.
Figure 27. Random Control Registers Single-Byte Read
S T A R T S 0 0
By Master
Control Registers Slave Address
Control Register Address
Control Registers Slave Address
A
S T 0 P P
SDA Line By nvSRAM
1
1 A2 A1 X
0
Sr 0
0
1
1
A2 A1 X
1
Data Byte A A A
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Figure 28. Random Control Registers Multi-Byte Read
S T A R T S 0 0
By Master
Control Registers Slave Address
Control Register Address
Control Registers Slave Address
A
By nvSRAM A A S T 0 P P A A
Data Byte
Data Byte N
Serial Number
Serial number is an 8 byte memory space provided to the user to uniquely identify this device. It typically consists of a two byte customer ID, followed by five bytes of unique serial number and one byte of CRC check. However, nvSRAM does not calculate the CRC and it is up to the user to utilize the eight byte memory space in the desired format. The default values for the eight byte locations are set to `0x00'. Serial Number Write The serial number can be accessed through the Control Registers Slave Device. To write the serial number, master transmits the Control Registers Slave address after the START condition and writes to the address location from 0x01 to 0x08. The content of Serial Number registers is secured to nonvolatile memory on the next STORE operation. If AutoStore is enabled, nvSRAM automatically stores the Serial number in the nonvolatile memory on power-down. However, if AutoStore is disabled, user must perform a STORE operation to secure the contents of Serial Number registers. Note If the serial number lock (SNL) bit is not set, the serial number registers can be re-written regardless of whether or not a STORE has happened. Once the serial number lock bit is set, no writes to the serial number registers are allowed. If the master tries to perform a write operation to the serial number registers when the lock bit is set, a NACK is returned and write will not be performed.
Serial Number Lock After writes to Serial Number registers is complete, master is responsible for locking the serial number by setting the serial number lock bit to `1' in the Memory Control Register (0x00). The content of Memory Control Register and serial number are secured on the next STORE operation (STORE or AutoStore). If AutoStore is not enabled, user must perform STORE operation to secure the lock bit status. If a STORE was not performed, the serial number lock bit will not survive power cycle. The serial number lock bit and 8 - byte serial number is defaults to `0' at power-up. Serial Number Read Serial number can be read back by a read operation of the intended address of the Control Registers Slave. The Control Registers Device loops back from the last address (excluding the Command Register) to 0x00 address location while performing burst read operation. The serial number resides in the locations from 0x01 to 0x08. Even if the serial number is not locked, a serial number read operation will return the current values written to the serial number registers. Master may perform a serial number read operation to confirm if the correct serial number is written to the registers before setting the lock bit.
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~ ~
SDA Line
1
1 A2 A1
X
0
Sr 0
0
1
1
A2 A1 X
1
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CY14C101J CY14B101J, CY14E101J
Device ID Read
Device ID is a 4 byte code consisting of JEDEC assigned manufacturer ID, product ID, density ID, and die revision. These registers are set in factory and are read only registers for the user.
Table 7. Device ID
Bits #of Bits Device CY14C101J1 CY14C101J2 CY14C101J3 CY14B101J1 CY14B101J2 CY14B101J3 CY14E101J1 CY14E101J2 CY14E101J3 31 - 21 (11 bits) Manufacture ID 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 00000110100 20 - 7 (14 bits) Product ID 00001001000001 00001101000000 00001101000001 00001001010001 00001101010000 00001101010001 00001001100001 00001101100000 00001101100001 6- 3 (4 bits) Density ID 0100 0100 0100 0100 0100 0100 0100 0100 0100 2-0 (3 bits) Die Rev 000 000 000 000 000 000 000 000 000
The device ID is divided into four parts as shown in Table 7: 1. Manufacturer ID (11 bits) This is the JEDEC assigned manufacturer ID for Cypress. JEDEC assigns the manufacturer ID in different banks. The first three bits of the manufacturer ID represent the bank in which ID is assigned. The next eight bits represent the manufacturer ID. Cypress manufacturer ID is 0x34 in bank 0. Therefore the manufacturer ID for all Cypress nvSRAM products is given as: Cypress ID - 000_0011_0100 2. Product ID (14 bits) The product ID for device is shown in the Table 7. 3. Density ID (4 bits) The 4 bit density ID is used as shown in Table 7 for indicating the 1 Mb density of the product. 4. Die Rev (3 bits) This is used to represent any major change in the design of the product. The initial setting of this is always 0x0.
Executing Register
Commands
Using
Command
The Control Registers Slave allows different commands to be executed by writing the specific command byte in the command register (0xAA). The command byte codes for each command are specified in Table 6. During the execution of these commands the device is not accessible and returns NACK if any of the two slave devices is selected. If an invalid command is sent by the master, nvSRAM responds with a NACK indicating that command was not successful. The address latch of this slave continues to point to the command register address. This location can be read back to identify the data byte that was written to the nvSRAM. A read access to the command register is allowed and a burst read would loop back to the first address in the array (0x00). During execution of any command, the address counter retain their value.
Figure 29. Command Execution using Command Register
By Master
S T A R T S 0 0
Control Register Slave Address
Command Register Address
Command Byte
S T O P P
SDA Line By nvSRAM
1
1 A2 A1 X
0
1
0
1
0
1
0
1
0
A
A
A
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Best Practices
nvSRAM products have been used effectively for over 26 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:
Power-up boot firmware routines should rewrite the nvSRAM into the desired state (for example, AutoStore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this max VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection.
The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
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CY14C101J CY14B101J, CY14E101J
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ -65 C to +150 C Maximum accumulated storage time At 150 C ambient temperature........ ............... 1000 h At 85 C ambient temperature..................... 20 Years Ambient temperature with power applied ........................................... -55 C to +150 C Supply voltage on VCC relative to VSS CY14C101J: VCC = 2.4 V to 2.6 V .....-0.5 V to +3.1 V CY14B101J: VCC = 2.7 V to 3.6 V .....-0.5 V to +4.1 V CY14E101J: VCC = 4.5 V to 5.5 V .....-0.5 V to +7.0 V DC voltage applied to outputs in High-Z State..................................... -0.5 V to VCC + 0.5 V Input voltage ........................................ -0.5 V to VCC + 0.5 V
Transient voltage (<20 ns) on any pin to ground potential .................. -2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 C) .................................................. 1.0 W Surface mount lead soldering temperature (3 seconds) .......................................... +260 C DC output current (1 output at a time, 1s duration). .... 15 mA Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, Method 3015) Latch up current..................................................... > 140 mA
Operating Range
Product CY14B101J CY14E101J Range Ambient Temperature VCC 2.4 V to 2.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V CY14C101J Industrial -40 C to +85 C
DC Electrical Characteristics
Over the Operating Range Parameter Description VCC Power supply Test Conditions CY14C101J CY14B101J CY14E101J ICC1 ICC2 ICC3 ICC4 ISB IZZ IIX Average VCC current Average VCC current during STORE fSCL = 3.4 MHz; Values obtained without output loads (IOUT = 0 mA) All inputs don't care, VCC = Max Average current for duration tSTORE Min 2.4 2.7 4.5 - - - Typ[3] 2.5 3.0 5.0 - - - Max 2.6 3.6 5.5 1 2 1 Unit V V V mA mA mA
Average VCC current fSCL = All inputs cycling at CMOS levels. 100 kHz; Values obtained without output loads (IOUT = 0 mA) VCC = VCC (Typ), 25 C Average VCAP current during AutoStore Cycle VCC standby current Sleep mode current All inputs don't care. Average current for duration tSTORE SCL > (VCC - 0.2 V). VIN < 0.2 V or > (VCC - 0.2 V). Standby current level after nonvolatile cycle is complete. Inputs are static. fSCL = 0 MHz. tSLEEP time after SLEEP Instruction is Issued. All inputs are static and configured at CMOS logic level.
- -
- -
3 150
mA A
- -1 -100 -1
- - - - -
8 +1 +1 +1 7
A A A A pF
Input current in each I/O pin 0.1 VCC < Vi < 0.9 VCCmax (except HSB) Input current in each I/O pin (for HSB)
IOZ Ci
Output leakage current Capacitance for each I/O pin Capacitance measured across all input and output signal pin and VSS.
-
Note 3. Typical values are at 25 C, VCC = VCC (Typ). Not 100% tested.
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DC Electrical Characteristics (continued)
Over the Operating Range Parameter Description VIH VIL VOL Rin[4] Vhys VCAP Input HIGH voltage Input LOW voltage Output LOW voltage Input resistance (WP, A2, A1) Hysteresis of Schmitt trigger inputs Storage capacitor VCC = 2.4 V to 2.6 V Storage Capacitor VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V Between VCAP pin and VSS Between VCAP pin and VSS IOL= 3 mA For VIN = VIL (Max) For VIN = VIH (Max) Test Conditions Min 0.7 Vcc - 0.5 0 50 1 0.05 VCC 170 42 Typ[3] - - - - - - 220 47 Max VCC + 0.5 0.3 Vcc 0.4 - - - 270 180 Unit V V V K M V F F
Data Retention and Endurance
Parameter DATAR NVC Data retention Nonvolatile STORE operations Description Min 20 1,000 Unit Years K
Thermal Resistance
Parameter[5] Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 8-SOIC 101.08 37.86 16-SOIC 56.68 32.11 Unit C/W C/W
JA
JC
Notes 4. The input pull-down circuit is stronger (50 K) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH. 5. These parameters are guaranteed by design and are not tested.
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Figure 30. AC Test Loads and Waveforms For 2.5 V (CY14C101J) For 3.0 V (CY14B101J) For 5.0 V (CY14E101J)
2.5 V
3.0 V
5.0 V
700 OUTPUT 100 pF OUTPUT
867 OUTPUT 100 pF
1.6 K
50 pF
AC Test Conditions
Input pulse levels Input rise and fall times (10% - 90%) Input and output timing reference levels CY14C101J 0 V to 2.5 V 10 ns 1.25 V CY14B101J 0 V to 3 V 10 ns 1.5 V CY14E101J 0 V to 5 V 10 ns 2.5 V
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AC Switching Characteristics
Parameter fSCL tSU; STA tHD;STA tLOW tHIGH tSU;DATA tHD;DATA tDH tr
[7]
Description Clock frequency, SCL Setup time for Repeated START condition Hold time for START condition LOW period of the SCL HIGH period of the SCL Data In setup time Data hold time (In/Out) Data Out hold time Rise time of SDA and SCL Fall time of SDA and SCL Setup time for STOP condition Data output valid time ACK output valid time Output fall time from VIHmin to VILmax Bus free time between STOP and next START condition Pulse width of spikes that must be suppressed by input filter
3.4 MHz[6] Min - 160 160 160 60 10 0 0 - - 160 - - - 0.3 - Max 3400 - - - - - - - 80 80 - 130 130 80 - 5
1 MHz[6] Min - 250 250 500 260 100 0 0 - - 250 - - - 0.5 - Max 1000 - - - - - - - 120 120 - 400 400 120 - 50
400 kHz[6] Min - 600 600 1300 600 100 0 0 - - 600 - - - 1.3 - Max 400 - - - - - - - 300 300 - 900 900 300 - 50
Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns us ns
tf[7] tSU;STO tVD;DATA tVD;ACK tOF tSP
[7]
tBUF
Figure 31. Timing Diagram
SDA
~ ~
tr t LOW t SU;DATA
~ ~
~ ~
~ ~
t HD;STA
t SP
tf
t BUF
SCL
~ ~ ~ ~
t HD;STA t HD;DATA t HIGH t SU;STA tr tf t SU;STO
S
Sr
P
S
Note 6. Bus Load (Cb) Considerations; Cb < 500 pF for I2C clock frequency (SCL) 100/400/1000 KHz; Cb < 100 pF for SCL at 3.4 MHz. 7. These parameters are guaranteed by design and are not tested.
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nvSRAM Specifications
Parameter tFA [8] Power-Up RECALL duration Description Min Max 40 20 20 8 25 Unit ms ms ms ms ns s V V V s V ns ms ms ms ms s
CY14C101J CY14B101J CY14E101J
- - - - - 150
tSTORE [9]
STORE cycle duration Time allowed to complete SRAM write cycle VCC rise time Low voltage trigger level
tDELAY[10] tVCCRISE[11]
-
2.35 2.65 4.40 5 1.9 500 40 20 20 8 100
VSWITCH
CY14C101J CY14B101J CY14E101J
- - - - - -
tLZHSB
[11]
HSB high To nvSRAM active time HSB output disable voltage HSB HIGH active time Time for nvSRAM to wake up from SLEEP mode
VHDIS[11] tWAKE
tHHHD[11]
CY14C101J CY14B101J CY14E101J
- - - - -
tSLEEP tSB
Time to enter low power mode after issuing SLEEP instruction Time to enter into standby mode after issuing STOP condition
Figure 32. AutoStore or Power-Up RECALL[12]
VCC VSWITCH VHDIS
t VCCRISE
13
tHHHD
Note 9
tSTORE tHHHD
Note
9
tSTORE
13
Note HSB OUT
Note tDELAY
AutoStore
tLZHSB tDELAY
tLZHSB
POWERUP RECALL Read & Write Inhibited (RWI) POWER-UP RECALL
tFA
tFA
Read & Write
BROWN OUT AutoStore
POWER-UP RECALL
Read & Write
POWER DOWN AutoStore
Notes 8. tFA starts from the time VCC rises above VSWITCH. 9. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 10. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 11. These parameters are guaranteed by design and are not tested. 12. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 13. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
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Software Controlled STORE/RECALL Cycles
Parameter tRECALL tSS[14, 15] Description RECALL duration Software sequence processing time CY14X101J Min
- -
Max 600 500
Unit s s
Figure 33. Software STORE/RECALL Cycle[15]
DATA OUTPUT BY MASTER
nvSRAM Control Slave Address
Command Reg Address
Command Byte (STORE/RECALL)
acknowledge (A) by Slave
acknowledge (A) by Slave
acknowledge (A) by Slave
SCL FROM MASTER
1 S
2
8
9
1
2
8
9
1
2
8
9 P
START condition RWI
STOP condition
t STORE / t
RECALL
Figure 34. AutoStore Enable/Disable Cycle
DATA OUTPUT BY MASTER
nvSRAM Control Slave Address
Command Reg Address
Command Byte (ASENB/ASDISB)
acknowledge (A) by Slave
acknowledge (A) by Slave
acknowledge (A) by Slave
SCL FROM MASTER
1 S
2
8
9
1
2
8
9
1
2
8
9 P
START condition RWI
STOP condition
t SS
Notes 14. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command. 15. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-54050 Rev. *D
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Hardware STORE Cycle
Parameter tPHSB Description Hardware STORE pulse width Figure 35. Hardware STORE Cycle[16] CY14X101J Min 15 Max
-
Unit ns
Write Latch set
HSB (IN) tDELAY HSB (OUT)
tSTORE
~ ~
tPHSB
tHHHD
~ ~
tLZHSB
RWI
Write Latch not set
HSB (IN)
~ ~
tPHSB
HSB pin is driven HIGH to VCC only by Internal 100 K resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW.
HSB (OUT)
tDELAY
RWI
Note 16. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated.
Document #: 001-54050 Rev. *D
~ ~
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Ordering Information
Ordering Code CY14C101J1-SXIT CY14C101J1-SXI CY14C101J2-SXIT CY14C101J2-SXI CY14C101J3-SFXIT CY14C101J3-SFXI CY14B101J1-SXIT CY14B101J1-SXI CY14B101J2-SXIT CY14B101J2-SXI CY14B101J3-SFXIT CY14B101J3-SFXI CY14E101J1-SXIT CY14E101J1-SXI CY14E101J2-SXIT CY14E101J2-SXI CY14E101J3-SFXIT CY14E101J3-SFXI Package Diagram 51-85066 51-85066 51-85066 51-85066 51-85022 51-85022 51-85066 51-85066 51-85066 51-85066 51-85022 51-85022 51-85066 51-85066 51-85066 51-85066 51-85022 51-85022 Package Type 8-pin SOIC (with WP) 8-pin SOIC (with WP) 8-pin SOIC (with VCAP) 8-pin SOIC (with VCAP) 16-pin SOIC (with WP, VCAP and HSB) 16-pin SOIC (with WP, VCAP and HSB) 8-pin SOIC (with WP) 8-pin SOIC (with WP)) 8-pin SOIC (with VCAP) 8-pin SOIC (with VCAP) 16-pin SOIC (with WP, VCAP and HSB) 16-pin SOIC (with WP, VCAP and HSB) 8-pin SOIC (with WP) 8-pin SOIC (with WP) 8-pin SOIC (with VCAP) 8-pin SOIC (with VCAP) 16-pin SOIC (with WP, VCAP and HSB) 16-pin SOIC (with WP, VCAP and HSB) Operating Range Industrial
All these parts are Pb-free. This table contains Preliminary information. Contact your local Cypress sales representative for availability of these parts.
Document #: 001-54050 Rev. *D
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Ordering Code Definitions
CY 14 C 101 J 1 - S X I T Option: T - Tape and Reel Blank - Std. Pb-free Package: SX - 8 SOIC SF - 16 SOIC
Temperature: I - Industrial (-40 to 85 C)
1 - With WP 2 - With VCAP 3 - With WP, VCAP and HSB
J - Serial (I2C) nvSRAM Density: Voltage: C - 2.5 V B - 3.0 V E - 5.0 V 14 - nvSRAM 101 - 1 Mb
Cypress
Document #: 001-54050 Rev. *D
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Package Diagrams
Figure 36. 8-Pin (150 mil) SOIC Package (51-85066)
51-85066 *D
Document #: 001-54050 Rev. *D
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Package Diagrams (continued)
Figure 37. 16-Pin (300 mil) SOIC (51-85022)
51-85022 *C
Document #: 001-54050 Rev. *D
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Acronyms
Acronym ACK CMOS CRC EIA I2C I/O JEDEC nvSRAM NACK RWI RoHS SNL SCL SDA SOIC WP Acknowledge Complementary Metal Oxide Semiconductor Cyclic Redundancy Check Electronic Industries Alliance Inter-Integrated Circuit Bus Input/Output Joint Electron Devices Engineering Council nonvolatile Static Random Access Memory No acknowledge Read and Write Inhibited Restriction of Hazardous Substances Serial Number Lock Serial Clock Line Serial Data Line Small Outline Integrated Circuit Write protect Description
Document Conventions
Units of Measure
Symbol C Hz kbit kHz K A mA F MHz s ms ns pF V W Hertz 1024 bits kilohertz kilo ohms microamperes milliampere microfarads megahertz microseconds millisecond nanoseconds picofarads volts ohms watts Unit of Measure degrees Celsius
Document #: 001-54050 Rev. *D
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PRELIMINARY
CY14C101J CY14B101J, CY14E101J
Document History Page
Document Title: CY14C101J, CY14B101J, CY14E101J 1 Mbit (128 K x 8) Serial (I2C) nvSRAM Document Number: 001-54050 Rev. ** *A ECN No. 2754627 2860397 Submission Date 08/21/09 01/20/2010 Orig. of Change GVCH GVCH New Data Sheet Changed Vcc range for CY14C101I from 2.3 - 2.7V to 2.4-2.6V Removed 16-SOIC 150 mil package option Added 16-SOIC 300 mil package option Added 3.4MHz bus frequency related information Changed IOL min value from 20 mA to 3mA Changed tLOW min value from 400ns to 500ns for 1MHz Changed tLOW min value from 600ns to 1300ns for 400 KHz Changed tHIGH min value from 400ns to 260ns Changed tDH min value from 50ns to 0ns Updated tr max value. Removed tSP min value Changed datasheet status from "Advance" to "Preliminary" Changed data sheet title from CY14C101J, CY14B101J, CY14E101J 1 Mbit (128K x 8) Serial (I2C) nvSRAM with Real Time Clock (RTC) to CY14C101J, CY14B101J, CY14E101J 1 Mbit (128K x 8) Serial (I2C) nvSRAM Updated logic block diagram Updated Pinouts Updated Pin Definitions Complete content write Changed ICC4 value from 2 mA to 3 mA Added IOZ and Ci parameter in DC Electrical Characteristics Removed IOL parameter in DC Electrical Characteristics Changed VCAP value from for VCC=2.4V-2.6V 1. Changed min value from 100 uF to 170 uF 2. Changed typ value from 150 uF to 220 uF 3. Changed max value from 330 uF to 270 uF Changed VCAP value from for VCC=2.7V-3.6V and VCC=4.5-5.5 V 1. Changed min value from 40 uF to 42 uF Added Data Retention and Endurance Table Added Thermal Resistance Table Added AC Test Conditions Table Added Figures Added Software Controlled STORE/RECALL Cycles Table Added Hardware STORE Cycle Table Added tFA for VCC=2.4V-2.6V Added tWAKE for VCC=2.4V-2.6V Added tSB parameter Changed VSWITCH from 4.45 V to 4.40V for VCC = 4.5 V to 5.5 V Updated tRECALL value from 200 us to 300 us Changed tSS value from 100 to 200 s Added tPHSB parameter Updated Ordering Information Updated tSP max value from 10 ns to 5 ns for 3.4 MHz Updated tSS value from 200 us to 500 us Updated tRECALL value from 300 us to 600 us Added Units of Measure table Hardware STORE and HSB pin Operation: Added more clarity on HSB pin operation Updated tLZHSB parameter description Fixed typo in Figure 32. Description of Change
*B
2963131
06/28/2010
GVCH
*C
3084950
11/12/2010
GVCH
*D
3147585
01/19/2011
GVCH
Document #: 001-54050 Rev. *D
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PRELIMINARY
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
CY14C101J CY14B101J, CY14E101J
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
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PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-54050 Rev. *D
Revised January 19, 2011
Page 32 of 32
All products and company names mentioned in this document are the trademarks of their respective holders.
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